1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a two step process for forming a doped polysilicon self aligned contact plug with low contact resistance.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. However, contact resistance is a key limitation of current SAC processes, particularly as processing speed in creases. High contact resistance and variability in contact resistance from contact to contact can reduce device life and cause reliability problems.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,807,779 (Liaw) shows a polysilicon self aligned contact process.
U.S. Pat. No. 5,763,303 (Liaw) shows a rapid thermal chemical vapor deposition procedure for a self aligned, polycide contact structure, wherein load and evacuation steps are performed in-situ at room temperature, followed by poly and tungsten depositions.
U.S. Pat. No. 5,631,179 (Sung et al.) and U.S. Pat. No. 5,607,879 (Wuu et al.) teach self aligned contact processes.
U.S. Pat. No. 5,607,724 (Beinglass et al.) shows a wafer chamber which can be used for high temperature chemical vapor deposition of polycrystalline silicon.